Integrated circuits are formed from an extremely large number of small structures, which are layered one upon another in repetitively applied pattern transfer and pattern development operations. As the term is used herein, “integrated circuit” includes devices such as those formed on monolithic semiconducting substrates, such as those formed of group IV materials like silicon or germanium, or group III-V compounds like gallium arsenide, or mixtures of such materials. The term includes all types of devices formed, such as memory and logic, and all designs of such devices, such as MOS and bipolar. The term also comprehends applications such as flat panel displays, solar cells, and charge coupled devices.
When a new integrated circuit design is produced, it is first designed in a computerized model. From this computerized model, the reticles that are used for the pattern transfer processes (such as photolithographic processes) are created. Once the reticles have been fabricated, the pattern transfer processes are qualified, to determine the most desirable process to be used for each layer. Several important steps selectively occur during this qualification process. For example, for a given mask layer, different types of photoresist might be investigated to see how they perform for that mask layer. Each photoresist investigated might be applied at different thicknesses, bake times, etc.
By way of further example, other layers can also used in different pattern transfer processes, such as anti-reflective coatings (bottom anti-reflective coating and top anti reflective coating). Illumination parameters such as source type, source shape, and illumination wavelengths are additional variable parameters. With the complexities that are present in some patterns, optical correction might need to be applied to the pattern to ensure proper pattern transfer. There can also be different types of optical correction models applied to the pattern. Such different combinations of parameters are generally referred to as a “process” herein.
Further, each process for each reticle layer is also investigated for how well the process forms the integrated circuit pattern at different combinations of exposure and focus. Acceptable ranges of exposure and focus for a given process are generally referred to as the “process window.” Within the process window, the structures to be formed with a given reticle are properly constructed. Outside of the process window, at least some of the structures will exhibit some type of defect. A relatively larger process window indicates that there is greater latitude for variance of the exposure and focus parameters during processing, and is generally regarded as a good thing. A relatively smaller process window indicates that there is less latitude for variance of the exposure and focus parameters during processing, and is generally regarded as a bad thing.
Investigating the various processes and the windows for each process for each mask layer is a tremendously labor intensive undertaking, and thus is extremely expensive. However, this process is performed for every integrated circuit design that is put into production.
What is needed, therefore, is a system for reducing the amount of time required for qualifying the processes for new integrated circuit designs.